Renesas Network Card SH7362 User Guide

REJ10J1709-0100  
SuperHFamily E10A-USB Emulator  
Additional Document for User’s Manual  
Supplementary Information on Using the SH7362  
Renesas Microcomputer Development Environment System  
SuperHFamily  
E10A-USB for SH7362 HS7362KCU01HE  
Rev.1.00  
Revision Date: Aug. 20, 2007  
 
Notes regarding these materials  
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate  
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accuracy or completeness of the information contained in this document nor grants any license to any  
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out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,  
programs, algorithms, and application circuit examples.  
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4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and  
application circuit examples, is current as of the date this document is issued. Such information, however, is  
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(2) surgical implantations  
(3) healthcare intervention (e.g., excision, administration of medication, etc.)  
(4) any other purposes that pose a direct threat to human life  
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Contents  
Section 1 Connecting the Emulator with the User System................................1  
1.1 Components of the Emulator ............................................................................................1  
1.2 Connecting the Emulator with the User System ...............................................................2  
1.3 Installing the H-UDI Port Connector on the User System ................................................3  
1.4 Pin Assignments of the H-UDI Port Connector................................................................4  
1.5 Recommended Circuit between the H-UDI Port Connector and the MPU.......................8  
1.5.1 Recommended Circuit (36-Pin Type)..................................................................8  
1.5.2 Recommended Circuit (14-Pin Type)..................................................................10  
1.5.3 Recommended Circuit (38-Pin Type)..................................................................12  
Section 2 Software Specifications when Using the SH7362 .............................15  
2.1 Differences between the SH7362 and the Emulator .........................................................15  
2.2 Specific Functions for the Emulator when Using the SH7362..........................................20  
2.2.1 Event Condition Functions ..................................................................................20  
2.2.2 Trace Functions....................................................................................................28  
2.2.3 Notes on Using the JTAG (H-UDI) Clock (TCK) and AUD Clock (AUDCK)...38  
2.2.4 Notes on Setting the [Breakpoint] Dialog Box ....................................................38  
2.2.5 Notes on Setting the [Event Condition] Dialog Box and  
the BREAKCONDITION_SET Command ........................................................40  
2.2.6 Note on Setting the UBC_MODE Command......................................................40  
2.2.7 Note on Setting the PPC_MODE Command .......................................................40  
2.2.8 Performance Measurement Function ...................................................................41  
i
 
ii  
 
Section 1 Connecting the Emulator with the User System  
1.1  
Components of the Emulator  
The E10A-USB emulator supports the SH7362. Table 1.1 lists the components of the emulator.  
Table 1.1 Components of the Emulator  
Classi-  
fication Component  
Quan-  
tity  
Appearance  
Remarks  
Hard-  
ware  
Emulator box  
1
HS0005KCU01H:  
Depth: 65.0 mm, Width: 97.0 mm,  
Height: 20.0 mm, Mass: 72.9 g  
or  
HS0005KCU02H:  
Depth: 65.0 mm, Width: 97.0 mm,  
Height: 20.0 mm, Mass: 73.7 g  
User system interface  
cable  
1
1
14-pin type:  
Length: 20 cm, Mass: 33.1 g  
User system interface  
cable  
36-pin type:  
Length: 20 cm, Mass: 49.2 g  
(only for HS0005KCU02H)  
USB cable  
1
Length: 150 cm, Mass: 50.6 g  
HS0005KCU01SR,  
Soft-  
ware  
E10A-USB emulator setup  
program,  
1
SuperHTM Family E10A-  
USB Emulator User’s  
Manual,  
HS0005KCU01HJ,  
HS0005KCU01HE,  
Supplementary  
Information on Using the  
SH7362*, and  
HS7362KCU01HJ,  
HS7362KCU01HE,  
Test program manual for  
HS0005KCU01H and  
HS0005KCU02H  
HS0005TM01HJ, and  
HS0005TM01HE  
(provided on a CD-R)  
Note: Additional document for the MPUs supported by the emulator is included. Check the target  
MPU and refer to its additional document.  
1
 
1.2  
Connecting the Emulator with the User System  
To connect the E10A-USB emulator (hereinafter referred to as the emulator), the H-UDI port  
connector must be installed on the user system to connect the user system interface cable. When  
designing the user system, refer to an example of recommended connection between the connector  
and the MPU shown in this manual. In addition, read the E10A-USB emulator user's manual and  
hardware manual for the related device.  
Table 1.2 shows the type number of the emulator, the corresponding connector type, and the use of  
AUD function.  
Table 1.2 Type Number, AUD Function, and Connector Type  
Type Number  
Connector  
AUD Function  
Available  
HS0005KCU02H  
36-pin connector  
14-pin connector  
38-pin connector  
HS0005KCU01H, HS0005KCU02H  
HS0005KCU02H  
Not available  
Available  
The H-UDI port connector has the 36-pin, 14-pin, and 38-pin types as described below. Use them  
according to the purpose of the usage.  
1. 36-pin type (with AUD function)  
The AUD trace function is supported. A large amount of trace information can be acquired in  
realtime. The window trace function is also supported for acquiring memory access in the  
specified range (memory access address or memory access data) by tracing.  
2. 14-pin type (without AUD function)  
The AUD trace function cannot be used because only the H-UDI function is supported. Since  
the 14-pin type connector is smaller than the 36-pin type (1/2.5), the size of the area where the  
connector is installed on the user system can be reduced.  
3. 38-pin type (with AUD function)  
The AUD trace function is supported. As well as the 36-pin type, a large amount of trace  
information can be acquired in realtime. Since the 38-pin type connector is smaller than the  
36-pin type (1/2.5), the size of the area where the connector is installed on the user system can  
be reduced. To use the 38-pin type connector, however, an optional cable (HS0005ECK01H)  
is required.  
2
 
1.3  
Installing the H-UDI Port Connector on the User System  
Table 1.3 shows the recommended H-UDI port connectors for the emulator.  
Table 1.3 Recommended H-UDI Port Connectors  
Connector  
Type Number  
Manufacturer  
Specifications  
Screw type  
36-pin connector DX10M-36S  
Hirose Electric Co., Ltd.  
DX10M-36SE,  
Lock-pin type  
DX10G1M-36SE  
14-pin connector 2514-6002  
Minnesota Mining &  
Manufacturing Ltd.  
14-pin straight type  
38-pin Mictor type  
38-pin connector 2-5767004-2  
Tyco Electronics AMP K.K.  
Note: When designing the 36-pin connector layout on the user board, do not connect any  
components under the H-UDI connector. When designing the 14-pin connector layout on  
the user board, do not place any components within 3 mm of the H-UDI port connector.  
When designing the 38-pin connector layout on the user board, reduce cross-talk noise etc.  
by keeping other signal lines out of the region where the H-UDI port connector is situated.  
As shown in figure 1.1, an upper limit (5 mm) applies to the heights of components  
mounted around the user system connector.  
3
 
E10A-USB optional 38-pin  
user system interface cable  
50 mm  
37  
1
2
38  
5 mm  
2-5767004-2  
: Area to be kept free of other components  
H-UDI port connector (top view)  
Target system  
Figure 1.1 Restriction on Component Mounting  
1.4  
Pin Assignments of the H-UDI Port Connector  
Figures 1.2 through 1.4 show the pin assignments of the 36-pin, 14-pin, and 38-pin H-UDI port  
connectors, respectively.  
Note: Note that the pin number assignments of the H-UDI port connector shown on the  
following pages differ from those of the connector manufacturer.  
4
 
Pin  
No.  
SH7362  
Pin No.  
Pin  
No. Signal  
Input/  
Output  
Input/  
Output  
SH7362  
Pin No.  
*1  
*1  
Note  
Note  
Signal  
TMS  
M15  
Input  
Input  
Input  
AUDCK  
1
Output  
19  
20  
21  
22  
23  
24  
K13  
L13  
K14  
K15  
N13  
GND  
2
3
4
5
6
GND  
*2  
*4  
Output  
/TRST  
(GND)  
L14  
L15  
M13  
AUDATA0  
GND  
Output  
Output  
TDI  
AUDATA1  
GND  
GND  
TDO  
Output  
AUDATA2  
25  
26  
7
8
GND  
GND  
Input/  
output  
/ASEBRK /  
BRKACK  
*2  
Output  
Output  
27  
AUDATA3  
M14  
M16  
9
28  
29  
30  
GND  
UVCC  
GND  
10  
11  
GND  
*2  
Output  
/AUDSYNC  
12  
13  
GND  
N.C.  
*2  
/RESETP  
/RESETA  
Output  
Output  
D15  
D12  
User reset  
*5  
31  
32  
33  
34  
35  
36  
GND  
14  
15  
16  
17  
18  
GND  
*3  
GND  
Output  
N.C.  
GND  
TCK  
GND  
GND  
N.C.  
GND  
J17  
Input  
Notes:  
1. Input to or output from the user system.  
2. The symbol (/) means that the signal is active-low.  
3. The emulator monitors the GND signal of the user system and detects whether or  
not the user system is connected.  
4. When the user system interface cable is connected to this pin and the MPMD pin is  
set to 0, do not connect to GND but to the MPMD pin directly.  
5. Connect /RESETP and /RESETA to the user system if required, as shown in figure 1.5.  
Edge of the board  
(connected to the connector)  
H-UDI port connector  
(top view)  
4
+0.1  
0
+0.1  
36  
2
φ
φ
0.7  
2.8  
0
(Pin 1 mark)  
3
35  
1
1.27  
M2.6 x 0.45  
4.09  
21.59  
37.61  
43.51  
: Pattern inhibited area  
H-UDI port connector (top view)  
H-UDI port connector (front view)  
Unit: mm  
Figure 1.2 Pin Assignments of the H-UDI Port Connector (36 Pins)  
5
 
Input/  
SH7362  
Pin No. Signal  
Output*1 Pin No.  
Note  
J17  
L13  
K15  
N13  
1
2
3
4
Input  
TCK  
*2  
*2  
Input  
/TRST  
TDO  
Output  
Input/  
output  
Input  
/ASEBRK  
/BRKACK  
TMS  
K13  
K14  
D15  
D12  
5
6
7
Input  
TDI  
Output  
Output  
User reset  
*2  
*4  
/RESETP  
/RESETA  
N.C.  
*5  
8
9
(GND)  
UVCC  
GND  
11  
Output  
Output  
10, 12,  
and 13  
14  
*3  
GND  
1. Input to or output from the user system.  
Notes:  
2. The symbol (/) means that the signal is active-low.  
3. The emulator monitors the GND signal of the user  
system and detects whether or not the user system  
is connected.  
4. When the user system interface cable is connected to  
this pin and the MPMD pin is set to 0, do not connect to  
GND but to the MPMD pin directly.  
5. Connect /RESETP and /RESETA to the user system  
if required, as shown in figure 1.6.  
Pin 1 mark  
H-UDI port connector (top view)  
25.0  
23.0  
6 x 2.54 = 15.24  
H-UDI port connector  
(top view)  
(2.54)  
Pin 8  
Pin 1  
Pin 14  
Pin 7  
0.45  
Unit: mm  
Pin 1 mark  
Figure 1.3 Pin Assignments of the H-UDI Port Connector (14 Pins)  
6
 
Pin  
No.  
Pin  
No.  
SH7362  
Pin No.  
Input/  
Output  
SH7362  
Pin No.  
Input/  
*1  
*1  
Output  
Signal  
Signal  
Note  
Note  
N.C.  
1
2
3
4
5
6
7
8
N.C.  
N.C.  
20  
21  
22  
23  
24  
25  
26  
27  
*2  
Input  
/TRST  
N.C.  
L13  
*4  
*3  
MPMD (GND)  
N.C.  
N.C.  
/UCON (GND)  
AUDCK  
AUDATA3  
N.C.  
Output  
Output  
M14  
M13  
Output  
M15  
N13  
N.C.  
AUDATA2  
N.C.  
/ASEBRK/  
BRKACK  
Input/  
Output  
*2  
/RESETP  
/RESETA  
28  
AUDATA1  
*2  
9
D15  
D12  
Output  
User reset  
Output  
L15  
29  
30  
31  
32  
33  
34  
35  
36  
37  
N.C.  
10  
11  
12  
13  
N.C.  
TDO  
Output  
Output  
AUDATA0  
N.C.  
Output  
Output  
K15  
L14  
UVCC_AUD  
N.C.  
*2  
M16  
/AUDSYNC  
N.C.  
14  
15  
UVCC  
TCK  
Output  
Input  
J17  
K13  
K14  
N.C.  
16  
N.C.  
N.C.  
Input  
Input  
N.C.  
17  
18  
19  
TMS  
N.C.  
TDI  
N.C.  
38  
N.C.  
1. Input to or output from the user system.  
Notes:  
2. The symbol (#) means that the signal is active-low.  
3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected.  
4. When the user system interface cable is connected to this pin and the MPMD pin is set to 0, do not connect to  
GND but to the MPMD pin directly.  
5. The GND bus lead at the center of the H-UDI port connector must be grounded.  
6. Connect /RESETP and /RESETA to the user system if required, as shown in figure 1.7.  
37  
1
6.91  
38  
2
Unit: mm  
25.4  
H-UDI port connector (top view)  
Figure 1.4 Pin Assignments of the H-UDI Port Connector (38 Pins)  
7
 
1.5  
Recommended Circuit between the H-UDI Port Connector and the  
MPU  
1.5.1  
Recommended Circuit (36-Pin Type)  
Figure 1.5 shows a recommended circuit for connection between the H-UDI and AUD port  
connectors (36 pins) and the MPU when the emulator is in use.  
Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector.  
2. The MPMD pin must be 0 when the emulator is connected and 1 when the emulator is  
not connected, respectively.  
(1) When the emulator is used: MPMD = 0  
(2) When the emulator is not used: MPMD = 1  
Figure 1.5 shows an example of circuits that allow the MPMD pin to be GND (0)  
whenever the emulator is connected by using the user system interface cable.  
3. When a network resistance is used for pull-up, it may be affected by a noise. Separate  
TCK from other resistances.  
4. The /TRST pin must be at the low level for a certain period when the power is  
supplied whether the H-UDI is used or not. Reduce the power supplied to the /TRST  
pin by pulling the pin down by a resistance of 1 kilo-ohm and setting PUL15 = 0 in  
the PULCR register after a reset.  
5. The pattern between the H-UDI port connector and the MPU must be as short as  
possible. Do not connect the signal lines to other components on the board.  
6. Since the H-UDI and the AUD of the MPU operate with the VccQ, supply only the  
VccQ to the UVCC pin. Make the emulator’s switch settings so that the user power  
will be supplied (SW2 = 1 and SW3 = 1).  
7. The resistance values shown in figure 1.5 are for reference.  
8. For the pin processing in cases where the emulator is not used, refer to the hardware  
manual of the related MPU.  
9. For the AUDCK pin, guard the pattern between the H-UDI port connector and the  
MPU at GND level.  
8
 
When the circuit is connected as shown in figure 1.5, the switches of the emulator are set as SW2  
= 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperHTM  
Family E10A-USB Emulator User’s Manual.  
VccQ_SR = 2.85-V/1.8-V I/O power supply  
VccQ_MFI = 2.85-V/1.8-V I/O power supply  
VccQ = 2.85-V I/O power supply  
All pulled-up at 4.7 kΩ or more  
VccQ_SR  
VccQ_SR  
VccQ_SRVccQ_SR  
VccQ_SR  
VccQ_SR  
H-UDI port connector  
(36-pin type)  
SH7362  
AUDCK  
1
2
4
GND  
GND  
GND  
AUDCK  
AUDATA0  
AUDATA1  
3
5
AUDATA0  
AUDATA1  
AUDATA2  
6
8
7
GND AUDATA2  
GND AUDATA3  
9
10  
AUDATA3  
AUDSYNC  
12  
11  
13  
AUDSYNC  
N.C.  
GND  
GND  
GND  
GND  
GND  
(GND)  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
14  
16  
18  
20  
15  
17  
19  
N.C.  
TCK  
TMS  
TCK  
TMS  
21  
23  
22  
TRST  
TRST  
TDI  
24  
26  
28  
TDI  
25  
27  
TDO  
TDO  
ASEBRK  
/ BRKACK  
ASEBRK  
/BRKACK  
29  
31  
33  
35  
30  
32  
34  
36  
UVCC  
RESET  
*1  
RESETP  
RESETA  
1 kΩ  
GND  
N.C.  
Level-shift  
circuit  
*2  
*3  
MPMD  
Power-on reset signal  
Reset signal  
User system  
Figure 1.5 Recommended Circuit for Connection between the H-UDI Port Connector and  
MPU when the Emulator is in Use (36-Pin Type)  
Notes: 1. Do not use /RESETP in the emulator after the user system has been activated.  
When reset signals are used for debugging, use /RESETA.  
2. Fix /RESETA as high level when it is not used.  
9
 
3. When the voltage level of VccQ_SR (power supply for H-UDI and AUD) is 2.85 V  
and that of VccQ_MFI (power supply for /RESETA) is 1.8 V, a level-shift circuit is  
required as shown in the figure.  
1.5.2  
Recommended Circuit (14-Pin Type)  
Figure 1.6 shows a recommended circuit for connection between the H-UDI port connector (14  
pins) and the MPU when the emulator is in use.  
Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector.  
2. The MPMD pin must be 0 when the emulator is connected and 1 when the emulator is  
not connected, respectively.  
(1) When the emulator is used: MPMD = 0  
(2) When the emulator is not used: MPMD = 1  
Figure 1.6 shows an example of circuits that allow the MPMD pin to be GND (0)  
whenever the emulator is connected by using the user system interface cable.  
3. When a network resistance is used for pull-up, it may be affected by a noise. Separate  
TCK from other resistances.  
4. The /TRST pin must be at the low level for a certain period when the power is  
supplied whether the H-UDI is used or not. Reduce the power supplied to the /TRST  
pin by pulling the pin down by a resistance of 1 kilo-ohm and setting PUL15 = 0 in  
the PULCR register after a reset.  
5. The pattern between the H-UDI port connector and the MPU must be as short as  
possible. Do not connect the signal lines to other components on the board.  
6. Since the H-UDI of the MPU operates with the VccQ, supply only the VccQ to the  
UVCC pin. Make the emulator’s switch settings so that the user power will be  
supplied (SW2 = 1 and SW3 = 1).  
7. The resistance values shown in figure 1.6 are for reference.  
8. For the pin processing in cases where the emulator is not used, refer to the hardware  
manual of the related MPU.  
10  
 
When the circuit is connected as shown in figure 1.6, the switches of the emulator are set as SW2  
= 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperHTM  
Family E10A-USB Emulator User’s Manual.  
VccQ_SR = 2.85-V/1.8-V I/O power supply  
VccQ_MFI = 2.85-V/1.8-V I/O power supply  
VccQ = 2.85-V I/O power supply  
All pulled-up at 4.7 kΩ or more  
VccQ_SR  
VccQ_SR  
VccQ_SR  
VccQ_SR  
VccQ_SR  
VccQ_SR  
H-UDI port connector  
(14-pin type)  
SH7362  
1
2
3
TCK  
TCK  
9
TRST  
TDO  
(GND)  
GND  
TRST  
TDO  
10  
ASEBRK  
/ BRKACK  
4
5
6
7
ASEBRK/BRKACK  
12  
TMS  
GND  
GND  
GND  
TMS  
TDI  
13  
14  
TDI  
RESET  
RESETP*1  
RESETA  
8
N.C.  
Level-shift  
circuit  
*2  
11  
1 kΩ  
UVCC  
*3  
MPMD  
Power-on reset signal  
Reset signal  
User system  
Figure 1.6 Recommended Circuit for Connection between the H-UDI Port Connector and  
MPU when the Emulator is in Use (14-Pin Type)  
Notes: 1. Do not use /RESETP in the emulator after the user system has been activated.  
When reset signals are used for debugging, use /RESETA.  
2. Fix /RESETA as high level when it is not used.  
3. When the voltage level of VccQ_SR (power supply for H-UDI and AUD) is 2.85 V  
and that of VccQ_MFI (power supply for /RESETA) is 1.8 V, a level-shift circuit is  
required as shown in the figure.  
11  
 
1.5.3  
Recommended Circuit (38-Pin Type)  
Figure 1.7 shows a recommended circuit for connection between the H-UDI and AUD port  
connectors (38 pins) and the MPU when the emulator is in use.  
Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector.  
2. The MPMD pin must be 0 when the emulator is connected and 1 when the emulator is  
not connected, respectively.  
(1) When the emulator is used: MPMD = 0  
(2) When the emulator is not used: MPMD = 1  
Figure 1.7 shows an example of circuits that allow the MPMD pin to be GND (0)  
whenever the emulator is connected by using the user system interface cable.  
When the MPMD pin is changed by switches, etc., ground pin 3. Do not connect this  
pin to the MPMD pin.  
3. When a network resistance is used for pull-up, it may be affected by a noise. Separate  
TCK from other resistances.  
4. The pattern between the H-UDI port connector and the MPU must be as short as  
possible. Do not connect the signal lines to other components on the board.  
5. The AUD signals (AUDCK, AUDATA3 to AUDATA0, and AUDSYNC) operate in  
high speed. Isometric connection is needed if possible. Do not separate connection nor  
connect other signal lines adjacently.  
6. Supply only the VCCQ voltage (I/O power supply) to the UVCC and UVCC_AUD  
pins because the H-UDI and AUD of the MPU operate at the VCCQ voltage,  
respectively. Make the emulator’s switch settings so that the user power will be  
supplied (SW2 = 1 and SW3 = 1).  
7. The resistance value shown in figure 1.7 is for reference.  
8. For the AUDCK pin, guard the pattern between the H-UDI port connector and the  
MPU at GND level.  
9. When the power is supplied, the TRST# pin must be low during a specified period  
regardless of whether or not the H-UDI is used.  
10. The GND bus lead at the center of the H-UDI port connector must be grounded.  
11. For the pin processing in cases where the emulator is not used, refer to the hardware  
manual of the related MPU.  
12  
 
When the circuit is connected as shown in figure 1.7, the switches of the emulator are set as SW2  
= 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperHTM  
Family E10A-USB Emulator User’s Manual.  
VccQ_SR = 2.85-V/1.8-V I/O power supply  
VccQ_MFI = 2.85-V/1.8-V I/O power supply  
VccQ = 2.85-V I/O power supply  
All pulled-up at 4.7 kΩ or more  
VccQ_SR  
VccQ_SR VccQ_SR VccQ_SR  
H-UDI port connector  
(38-pin type)  
SH7362  
AUDCK  
6
AUDCK  
32  
30  
AUDSYNC  
AUDSYNC  
AUDATA0  
AUDATA0  
AUDATA1  
AUDATA2  
28  
26  
24  
AUDATA1  
AUDATA2  
AUDATA3  
AUDATA3  
15  
17  
21  
19  
TCK  
TMS  
TCK  
TMS  
TRST  
TDI  
TRST  
TDI  
11  
8
TDO  
TDO  
ASEBRK  
/BRKACK  
ASEBRK  
/ BRKACK  
9
*1  
RESETP  
RESETA  
RESET  
Level-shift  
circuit  
*2  
3
*3  
MPMD(GND)  
UVCC  
MPMD  
14  
12  
1 kΩ  
Power-on reset signal  
Reset signal  
UVCC_AUD  
UCON (GND)  
5
GND  
N.C.  
GND bus leads  
1, 2, 4, 7,  
10, 13, 16, 18,  
20, 22, 23, 25, 27, 29,  
31, 33, 34, 35, 36, 37, 38  
User system  
Figure 1.7 Recommended Circuit for Connection between the H-UDI Port Connector and  
MPU when the Emulator is in Use (38-Pin Type)  
13  
 
Notes: 1. Do not use /RESETP in the emulator after the user system has been activated.  
When reset signals are used for debugging, use /RESETA.  
2. Fix /RESETA as high level when it is not used.  
3. When the voltage level of VccQ_SR (power supply for H-UDI and AUD) is 2.85 V  
and that of VccQ_MFI (power supply for /RESETA) is 1.8 V, a level-shift circuit is  
required as shown in the figure.  
14  
 
Section 2 Software Specifications when Using the SH7362  
2.1  
Differences between the SH7362 and the Emulator  
1. When the emulator system is initiated, it initializes the general registers and part of the control  
registers as shown in table 2.1. The initial values of the actual SH7362 registers are undefined.  
When the emulator is initiated from the workspace, a value to be entered is saved in a session.  
Table 2.1 Register Initial Values at Emulator Link Up  
Register  
R0 to R14  
R15 (SP)  
R0_BANK to R7_BANK  
PC  
Emulator at Link Up  
H'00000000  
H'A0000000  
H'00000000  
H'A0000000  
H'700000F0  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
H'000000F0  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
H'00000000  
SR  
GBR  
VBR  
MACH  
MACL  
PR  
SPC  
SSR  
RS  
RE  
MOD  
A0G, A1G  
A0, A1  
X0, X1  
Y0, Y1  
M0, M1  
DSR  
2. The emulator uses the H-UDI; do not access the H-UDI.  
15  
 
3. Low-Power States (Sleep, Software Standby, Module Standby, U Standby, and R Standby)  
For low-power consumption, the SH7362 has sleep, software standby, module standby, U  
standby, and R standby states.  
The sleep, software standby, U Standby, and R Standby states are switched using the SLEEP  
instruction. When the emulator is used, the sleep and software standby states can be cleared  
with either the normal clearing function or with the [STOP] button, and a break will occur.  
The power for some areas is turned off in U standby or R standby state and turned on in using  
the emulator.  
Note: The memory must not be accessed or modified in low-power state using the SLEEP  
instruction.  
4. Reset Signal (/RESETA)  
The SH7362 reset signal is only valid during emulation started with clicking the GO or STEP-  
type button.  
If the reset signal is enabled on the user system in command input wait state, it is not sent to  
the SH7362.  
Note: Do not break the user program when the /RESETA signal is being low or the bus-release  
request or wait control signal is being active. A TIMEOUT error will occur. If the bus-  
release request or wait control signal is fixed to active during break, a TIMEOUT error  
will occur at memory access.  
5. Direct Memory Access Controller (DMAC)  
The DMAC operates even when the emulator is used. When a data transfer request is  
generated, the DMAC executes DMA transfer.  
6. Memory Access during User Program Execution  
When a memory is accessed from the memory window, etc. during user program execution,  
the user program is resumed after it has stopped in the emulator to access the memory.  
Therefore, realtime emulation cannot be performed.  
The stopping time of the user program is as follows:  
Environment:  
Host computer: 800 MHz (Pentium® III)  
JTAG clock: 10 MHz (TCK clock)  
When a one-byte memory is read from the command-line window, the stopping time will be  
about 42 ms.  
16  
 
7. Memory Access during User Program Break  
The emulator can download the program for the flash memory area (for details, refer to section  
6.22, Download Function to the Flash Memory Area, in the SuperHTM Family E10A-USB  
Emulator User’s Manual). Other memory write operations are enabled for the RAM area.  
Therefore, an operation such as memory write or BREAKPOINT should be set only for the  
RAM area.  
8. Cache Operation during User Program Break  
When cache is enabled, the emulator accesses the memory by the following methods:  
At memory write: Writes through the cache, then issues a single write to outside. The LRU  
is not updated.  
At memory read: Reads memory from the cache. The LRU is not updated.  
Therefore, when memory read or write is performed during user program break, the cache state  
does not change.  
At breakpoint set: Disables the instruction cache.  
9. Port G  
The AUD pin is multiplexed as shown in table 2.2.  
Table 2.2 Multiplexed Functions  
Port Function 1  
Function 2  
G
G
PTG5 input/output (port)/IRQ7*  
AUDSYNC (AUD)  
AUDSYNC (AUD)  
PTG4 input/output (port)  
/SCIF_RXD/THPRTC4*  
G
G
G
G
PTG3 input/output (port)  
/SCIF_TXD/THPRTC3*  
AUDATA3 (AUD)  
AUDATA2 (AUD)  
AUDATA1 (AUD)  
AUDATA0 (AUD)  
PTG2 input/output (port)  
/SIM_CLK/THPRTC2*  
PTG1 input/output (port)  
/SIM_D/THPRTC1*  
PTG0 input/output (port)  
/SIM_RST/THPRTC0*  
Note: Function 1 can be used when the AUD pins of the device are not connected to the emulator.  
10. UBC  
When [User] is specified in the [UBC mode] list box in the [Configuration] dialog box, the  
UBC can be used in the user program.  
Do not use the UBC in the user program as it is used by the emulator when [EML] is specified  
in the [UBC mode] list box in the [Configuration] dialog box.  
17  
 
11. MFI  
When the MFI boot mode is used, be sure to activate the emulator by setting the MFIINT  
signal as a trigger for the MFI transfer from the base-band side.  
12. Memory Access during Break  
In the enabled MMU, when a memory is accessed and a TLB error occurs during break, it can  
be selected whether the TLB exception is controlled or the program jumps to the user  
exception handler in [TLB Mode] in the [Configuration] dialog box. When [TLB miss  
exception is enable] is selected, a “Communication Timeout error” will occur if the TLB  
exception handler does not operate correctly. When [TLB miss exception is disable] is selected,  
the program does not jump to the TLB exception handler even if a TLB exception occurs.  
Therefore, if the TLB exception handler does not operate correctly, a “Communication  
Timeout error” will not occur but the memory contents may not be correctly displayed.  
13. Loading Sessions  
Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading  
sessions. Thus the TCK value will be 1.25 MHz.  
14. [IO] Window  
Display and modification  
Do not change values of the User Break Controller because it is used by the emulator.  
For each RCLK watchdog timer register, there are two registers to be separately used for  
write and read operations.  
Table 2.3 RCLK Watchdog Timer Register  
Register Name  
RWTCSR(W)  
RWTCNT(W)  
RWTCSR(R)  
RWTCNT(R)  
Usage  
Write  
Write  
Read  
Read  
Register  
RCLK watchdog timer control/status register  
RCLK watchdog timer counter  
RCLK watchdog timer control/status register  
RCLK watchdog timer counter  
18  
 
The RCLK watchdog timer operates only when the user program is executed. Do not  
change the value of the frequency change register in the [IO] window or [Memory] window.  
The internal I/O registers can be accessed from the [IO] window. However, note the  
following when accessing the SDMR register of the bus-state controller. Before accessing  
the SDMR register, specify addresses to be accessed in the I/O-register definition file  
(SH7362.IO) and then activate the High-performance Embedded Workshop. After the I/O-  
register definition file is created, the MPU’s specifications may be changed. If each I/O  
register in the I/O-register definition file differs from addresses described in the hardware  
manual, change the I/O-register definition file according to the description in the hardware  
manual. The I/O-register definition file can be customized depending on its format. Note  
that, however, the E10A emulator does not support the bit-field function.  
Verify  
In the [IO] window, the verify function of the input value is disabled.  
15. Illegal Instructions  
If illegal instructions are executed by STEP-type commands, the emulator cannot go to the  
next program counter.  
16. [Reset CPU] and [Reset Go] in the [Debug] Menu  
When [Reset Mode] of the [Configuration] dialog box is set as [Auto], an H-UDI reset is  
issued by executing [Reset CPU] or [Reset Go]. For the H-UDI reset, the clock pulse  
generator and RCLK watchdog timer are not initialized.  
When [User] is selected and [Reset CPU] or [Reset Go] is executed, a reset signal input from  
the user system is waited; do not input /RESETP.  
19  
 
2.2  
Specific Functions for the Emulator when Using the SH7362  
2.2.1  
Event Condition Functions  
The emulator is used to set 12 event conditions (Ch1 to Ch12) and the software trace. Table 2.4  
lists the conditions of Event Condition.  
Table 2.4 Types of Event Conditions  
Event Condition Type  
Description  
Address bus condition (Address)  
Breaks when the SH7362 address bus value or the program  
counter value matches the specified value.  
Data bus condition (Data)  
Breaks when the SH7362 data bus value matches the  
specified value. Byte, word, or longword can be specified as  
the access data size.  
Bus state condition  
(Bus State)  
There are two bus state condition settings:  
Bus state condition: Breaks or acquires a trace when the  
data bus or the X-Bus or Y-Bus address bus of the SH7362  
is matched.  
Read/Write condition: Breaks or acquires a trace when the  
specified read/write condition is matched.  
Window address condition  
System bus  
Breaks or acquires a trace when the data in the specified  
memory range is accessed.  
Breaks or acquires a trace when the address or data on the  
system bus is matched.  
LDTLB instruction event condition  
Count  
Breaks when the SH7362 executes the LDTLB instruction.  
Breaks when the conditions set are satisfied the specified  
number of times.  
Branch trace condition  
(Branch trace)  
Breaks or acquires a trace when a branch occurs with the  
condition specified by the SH7362. (By default, trace  
acquisition is enabled).  
Software trace  
Action  
Selects whether or not the software trace is acquired.  
Selects the operation when a condition, such as setting a  
break, trace, or performance start or end, is matched.  
Table 2.5 lists the combinations of conditions that can be set under Ch1 to Ch12 and the software  
trace.  
20  
 
Table 2.5 Dialog Boxes for Setting Event Conditions  
Function  
Bus  
Window  
Address  
Address Data  
Bus Bus  
Dialog Condition Condition Condition (Bus  
State  
Branch  
ASID  
Condition Condition  
LDTLB  
Count  
Condition  
(Window System Instruction Condition (Branch Software  
Box  
(Address) (Data)  
(ASID)  
Status)  
address) Bus  
Break  
(Count)  
Trace)  
Trace  
Action  
[Event  
O
O
O
O
X
X
O
X
X
X
X
X
X
O
O
X
X
X
X
X
X
X
X
O
X
X
X
X
O
(B and  
P)  
Condition  
1] dialog  
box  
[Event  
O
O
O
O
O
X
O
X
X
O
O
X
X
X
X
X
O
O
X
X
X
X
X
X
X
O
X
O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
O
(B and  
P)  
Condition  
2] dialog  
box  
[Event  
O
(B and  
P)  
Condition  
3] dialog  
box  
[Event  
O
(B and  
P)  
Condition  
4] dialog  
box  
[Event  
O
Condition  
5] dialog  
box  
(B, T,  
and P)  
[Event  
X
O
Condition  
6] dialog  
box  
(B, T,  
and P)  
[Event  
X
Break  
fixed  
Condition  
7] dialog  
box  
[Event  
O
X
O
Condition  
8] dialog  
box  
(B, T,  
and P)  
21  
 
Table 2.5 Dialog Boxes for Setting Event Conditions (cont)  
Function  
Bus  
Window  
Address  
Address Data  
Bus Bus  
Dialog Condition Condition Condition (Bus  
State  
Branch  
ASID  
Condition Condition  
LDTLB  
Count  
Condition  
(Window System Instruction Condition (Branch Software  
Box  
(Address) (Data)  
(ASID)  
Status)  
address) Bus  
Break  
(Count)  
Trace)  
Trace  
Action  
[Event  
O
O
O
X
X
X
X
O
X
X
X
X
X
O
X
X
X
X
X
X
X
X
O
Condition  
9] dialog  
box  
(B, T,  
and P)  
[Event  
O
O
X
X
O
O
X
X
X
X
X
X
X
X
X
X
X
O
X
X
X
X
O
X
X
X
X
O
O
(B and  
P)  
Condition  
10] dialog  
box  
[Event  
O
(B and  
P)  
Condition  
11] dialog  
box  
[Event  
O
Condition  
12] dialog  
box  
(B, T,  
and P)  
[Software  
trace]  
Trace  
fixed  
dialog  
box  
Notes:  
1. O: Can be set in the dialog box.  
X: Cannot be set in the dialog box.  
2. For the Action item,  
B: Setting a break is enabled.  
T: Setting a trace is enabled.  
P: Setting a performance start or end condition is enabled.  
22  
 
Sequential Setting: In the emulator, sequential setting of an Event Condition is enabled.  
Table 2.6 Sequential Event Conditions  
Type  
Event Condition  
Description  
[CPU  
2 Channel Ch2 -> 1  
Halts a program when a condition is satisfied in the  
order of Event Condition 2, 1.  
An event condition must be set for Ch2 and Ch1.  
Sequential Sequential  
Event] Page  
Ch4 -> 3  
Halts a program when a condition is satisfied in the  
order of Event Condition 4, 3.  
An event condition must be set for Ch4 and Ch3.  
Ch6 -> 5  
Halts a program when a condition is satisfied in the  
order of Event Condition 6, 5.  
An event condition must be set for Ch6 and Ch5.  
Ch11 -> 10  
Ch3 -> 2 -> 1  
Halts a program when a condition is satisfied in the  
order of Event Condition 11, 10.  
An event condition must be set for Ch11 and Ch10.  
Many  
Channel  
Sequential  
Halts a program when a condition is satisfied in the  
order of Event Condition 3, 2, 1.  
An event condition must be set for Ch3, Ch2, and  
Ch1.  
Ch4 -> 3-> 2 -> 1  
Halts a program when a condition is satisfied in the  
order of Event Condition 4, 3, 2, 1.  
An event condition must be set for Ch4, Ch3, Ch2,  
and Ch1.  
Ch5 -> 4 -> 3-> 2 -> 1 Halts a program when a condition is satisfied in the  
order of Event Condition 5, 4, 3, 2, 1.  
An event condition must be set for Ch5, Ch4, Ch3,  
Ch2, and Ch1.  
Ch6 -> 5 -> 4 -> 3-> 2 Halts a program when a condition is satisfied in the  
-> 1  
order of Event Condition 6, 5, 4, 3, 2, 1.  
An event condition must be set for Ch6, Ch5, Ch4,  
Ch3, Ch2, and Ch1.  
Ch10 -> 6 -> 5 -> 4 -> Halts a program when a condition is satisfied in the  
3-> 2 -> 1  
order of Event Condition 10, 6, 5, 4, 3, 2, 1.  
An event condition must be set for Ch10, Ch6,  
Ch5, Ch4, Ch3, Ch2, and Ch1.  
Ch11 -> 10 -> 6 -> 5 -> Halts a program when a condition is satisfied in the  
4 -> 3-> 2 -> 1  
order of Event Condition 11, 10, 6, 5, 4, 3, 2, 1.  
An event condition must be set for Ch11, Ch10,  
Ch6, Ch5, Ch4, Ch3, Ch2, and Ch1.  
23  
 
Table 2.6 Sequential Event Conditions (cont)  
Type  
Event Condition  
Description  
[CPU  
CPU Extend  
Expands the [CPU Sequential Extend] page.  
The sequential setting is enabled with any  
combination.  
For details, refer to section 2.2.1, Sequential Break  
Extension Setting, in this manual.  
Sequential  
Event] Page  
(cont)  
[SystemBus SystemBus Ch9 -> 8  
Sequential Sequential  
Event] PageEvent  
Halts a program when a condition is satisfied for  
Event Condition 9, 8.  
An event condition must be set for Ch9 and Ch8.  
Ch8 -> 9  
Halts a program when a condition is satisfied for  
Event Condition 8, 9.  
An event condition must be set for Ch8 and Ch9.  
SystemBus  
Extend  
Expands the [SystemBus Sequential Extend] page.  
The sequential setting is enabled with any  
combination.  
For details, refer to section 2.2.1, Sequential Break  
Extension Setting, in this manual.  
24  
 
Sequential Break Extension Setting:  
Figure 2.1 [CPU Sequential Extend] Page  
(a) Indicates the channel name for setting conditions.  
(b) Selects a condition that is satisfied before the channel which sets up conditions.  
When a channel name is selected, it is required that the condition of the channel selected here  
must have already been satisfied.  
When [CPU Match flag] is selected, the CPU match flag must be set.  
When a condition is selected by the channel selected here, no break will occur.  
(c) When a condition is satisfied, the CPU match flag is set or cleared.  
When a program breaks, the CPU match flag is initialized.  
Set the event condition for each channel in the [Event Condition] dialog box; this also applies to  
the [SystemBus Sequential Extend] page.  
25  
 
Usage Example of Sequential Break Extension Setting: A tutorial program provided for the  
product is used as an example. For the tutorial program, refer to section 6, Tutorial, in the  
SuperHTM Family E10A-USB Emulator User’s Manual.  
The conditions of Event Condition are set as follows:  
1. Ch1  
Breaks address H’00001068 when the condition [Prefetch address break after executing] is  
satisfied.  
2. Ch2  
Breaks address H’00001058 when the condition [Prefetch address break after executing] is  
satisfied.  
3. Ch4  
Breaks address H’0000107a when the condition [Prefetch address break after executing] is  
satisfied.  
4. Ch10  
Breaks address H’00001086 when the condition [Prefetch address break after executing] is  
satisfied.  
Note: Do not set other channels.  
5. Set the [CPU Sequential Extend] page as shown in figure 2.1.  
Then, set the program counter and stack pointer (PC = H’00000800, R15 = H’00010000) in the  
[Registers] window and click the [Go] button. If this does not execute normally, issue a reset and  
execute the above procedures.  
The program is executed up to the condition of Ch10 and halted. Here, the condition is satisfied in  
the order of Ch2 -> 1 -> 4 -> 10.  
26  
 
Figure 2.2 [Source] Window at Execution Halted (Sequential Break)  
27  
 
2.2.2  
Trace Functions  
The emulator supports the trace functions listed in table 2.7.  
Table 2.7 Trace Functions  
Memory Output  
Trace  
Function  
Internal Trace  
AUD Trace  
Branch trace  
Supported (eight branches) Supported  
Supported  
Supported  
Supported  
Range memory access trace  
Software trace  
Supported (eight events)  
Supported (eight events)  
Supported  
Supported  
Table 2.8 shows the type numbers that the AUD function can be used.  
Table 2.8 Type Number and AUD Function  
Type Number  
AUD Function  
Not supported  
Supported  
HS0005KCU01H  
HS0005KCU02H  
28  
 
Branch Trace Functions: The branch source and destination addresses, their source lines, branch  
types, and types of accessed bus masters are displayed.  
[Setting Method]  
Select the check box in the [Branch] group box in the [Branch trace] page of the [Branch trace]  
dialog box that opens by double-clicking on the Ch12 (Branch) column of the [Eventpoint]  
window. The branch condition to be acquired can be set.  
Figure 2.3 [Branch trace] Dialog Box  
A branch trace can be acquired by selecting the [Acquire trace] check box of the [Action] page.  
Note: To cancel settings, select [Delete] from the popup menu that is opened by clicking on the  
Ch12 (Branch) column with the right-mouse button.  
29  
 
Range Memory Access Trace Functions: The memory access within the specified range is  
acquired by a trace. The read cycle, write cycle, or read/write cycle can be selected as the bus type,  
ASID value, or bus cycle for trace acquisition.  
[Setting Method]  
(i) To open the [Event condition 5] or [Event condition 6] dialog box, double-click on the Ch5  
(OA) or Ch6 (OA) column of the [Eventpoint] window.  
(ii) Remove the check mark of the [Don’t care] check box in the [Window address] page and enter  
the memory range to be set.  
Figure 2.4 [Window address] Page  
30  
 
(iii) Open the [ASID] page, remove the check mark of the [Don’t care] check box, and enter the  
ASID value to be set.  
When the ASID value is not set as a condition, do not remove the check mark of the [Don’t  
care] check box.  
(iv) Open the [Bus state] page and specify the bus type and bus cycle that are to be set.  
Figure 2.5 [Bus State] Page  
(v) Selecting the [Acquire trace] check box in the [Action] page enables acquiring memory  
access within the range.  
Note: To cancel settings, select the popup menu that is opened by clicking on the Ch5 (OA) or  
Ch6 (OA) column with the right-mouse button.  
31  
 
Software Trace Function:  
Note: This function can be supported with SHC/C++ compiler (manufactured by Renesas  
Technology Corp.; including OEM and bundle products) V6.0 or later.  
However, SHC/C++ compiler (including OEM and bundle products) V8.0 or later is  
needed when instructions other than those compatible with SH4 are output.  
When a specific instruction is executed, the PC value at execution and the contents of one general  
register are acquired by trace. Describe the Trace(x) function (x is a variable name) to be  
compiled and linked beforehand. For details, refer to the SuperHTM RISC engine C/C++ Compiler,  
Assembler, Optimizing Linkage Editor User’s Manual.  
When the load module is downloaded on the emulator and is executed while a software trace  
function is valid, the PC value that has executed the Trace(x) function, the general register value  
for x, and the source lines are displayed.  
To activate the software trace function, select the [Acquire Software trace] radio button in the  
[Software trace] dialog box that is opened by double-clicking on the software Trace column of the  
[Eventpoint] window.  
Note: To cancel settings, select the [Don’t care] radio button in the [Software trace] dialog box  
or select [Delete] from the popup menu that is opened by clicking on the software Trace  
column with the right-mouse button.  
Internal Trace Function: This function is activated by selecting the [Internal trace] radio button  
in the [Trace type] group box of the [Trace mode] page. Set the trace condition to be used.  
Notes: 1. If an interrupt is generated at the program execution start or end, including a step  
operation, the emulator address may be acquired. In such a case, the following  
message will be displayed. Ignore this address because it is not a user program address.  
*** EML ***  
2. If a completion-type exception occurs during exception branch acquisition, the next  
address to the address in which an exception occurs is acquired.  
3. Trace information cannot be acquired for the following branch instructions:  
The BF and BT instructions whose displacement value is 0  
Branch to H'A0000000 by reset  
32  
 
AUD Trace Function: This function is operational when the AUD pin of the device is connected  
to the emulator. It is activated by selecting the [AUD trace] radio button in the [Trace type] group  
box of the [Trace mode] page. Set the trace condition to be used.  
[Restrictions]  
Set bits 2 and 1 in register HIZCRB and bit 15 in register HIZCRC as 0 before activating the  
AUD trace function.  
When a reset signal is input during execution of the user program, no trace information can be  
acquired until a break occurs. If you wish to continue execution of the user program after a  
break, set bits 2 and 1 in register HIZCRB and bit 15 in register HIZCRC as 0.  
Do not execute [Reset Go] while using the AUD trace function. Use [Reset CPU] instead and  
set bits 2 and 1 in register HIZCRB and bit 15 in register HIZCRC as 0 before restarting the  
execution.  
Table 2.9 shows the AUD trace acquisition mode that can be set in each trace function.  
Table 2.9 AUD Trace Acquisition Mode  
Type  
Mode  
Description  
Continuous  
trace occurs  
Realtime trace  
When the next branch occurs while the trace information is  
being output, all the information may not be output. The user  
program can be executed in realtime, but some trace  
information will be lost.  
Non realtime trace When the next branch occurs while the trace information is  
being output, the CPU stops operations until the information  
is output. The user program is not executed in realtime.  
Trace buffer  
full  
Trace continue  
This function overwrites the oldest trace information to store  
the latest trace information.  
Trace stop  
After the trace buffer becomes full, the trace information is no  
longer acquired. The user program is continuously executed.  
33  
 
To set the AUD trace acquisition mode, click the [Trace] window with the right mouse button and  
select [Setting] from the pop-up menu to display the [Acquisition] dialog box. The AUD trace  
acquisition mode can be set in the [Trace Mode 1] or [Trace Mode 2] group box in the [Trace  
Mode] page of the [Acquisition] dialog box.  
Figure 2.6 [Trace Mode] Page  
34  
 
Notes on AUD Trace:  
1. When the trace display is performed during user program execution, the mnemonics, operands,  
or source is not displayed.  
2. The AUD branch trace function outputs the differences between newly output branch source  
addresses and previously output branch source addresses. The window trace function outputs  
the differences between newly output addresses and previously output addresses. If the  
previously output address is the same as the upper 16 bits, the lower 16 bits are output. If it  
matches the upper 24 bits, the lower 8 bits are output. If it matches the upper 28 bits, the lower  
4 bits are output.  
The emulator regenerates the 32-bit address from these differences and displays it in the  
[Trace] window. If the emulator cannot display the 32-bit address, it displays the difference  
from the previously displayed 32-bit address.  
3. If the 32-bit address cannot be displayed, the source line is not displayed.  
4. In the emulator, when multiple loops are performed to reduce the number of AUD trace  
displays, only the IP counts up.  
5. In the emulator, the maximum number of trace displays is 65534 lines (32767 branches).  
However, the maximum number of trace displays differs according to the AUD trace  
information to be output. Therefore, the above pointers cannot be always acquired.  
6. The AUD trace acquisition is not available when [User] is selected in the [UBC mode] list box  
of the [Configuration] dialog box. In this case, close the [Trace] window.  
7. Do not use the AUD full-trace mode for the VIO function.  
8. If a completion-type exception occurs during exception branch acquisition, the next address to  
the address in which an exception occurs is acquired.  
35  
 
Memory Output Trace Function: This function is activated by selecting the [Use Memory  
trace] radio button in the [Trace type] group box of the [Trace mode] page.  
In this function, write the trace data in the specified user memory range.  
Specify the start address to output a trace for the [Start] edit box in the [User memory area] group  
box, and the end address for the [End Address] edit box. Set the trace condition to be used.  
Table 2.10 shows the memory-output trace acquisition mode that can be set in each trace function.  
Table 2.10 Memory-Output Trace Acquisition Mode  
Type  
Mode  
Description  
Continuous  
trace occurs  
Realtime trace  
When the next branch occurs while the trace information is  
being output, all the information may not be output. The user  
program can be executed in realtime, but some trace  
information will be lost.  
Non realtime trace When the next branch occurs while the trace information is  
being output, the CPU stops operations until the information  
is output. The user program is not executed in realtime.  
Trace buffer  
full  
Trace continue  
This function overwrites the oldest trace information to store  
the latest trace information.  
Trace stop  
After the trace buffer becomes full, the trace information is no  
longer acquired. The user program is continuously executed.  
36  
 
To set the memory-output trace acquisition mode, click the [Trace] window with the right mouse  
button and select [Setting] from the pop-up menu to display the [Acquisition] dialog box. The  
AUD trace acquisition mode can be set in the [Trace Mode 1] or [Trace Mode 2] group box in the  
[Trace Mode] page of the [Acquisition] dialog box.  
Figure 2.7 [Trace Mode] Page  
37  
 
Notes: 1. The memory range for which trace is output is the address on the system bus and not  
supported for the MMU or cache.  
2. In the memory range for output, do not specify the ranges that the user program has  
been downloaded or the user program accesses.  
3. Do not select an internal RAM area as the memory range for output.  
4. The range for trace output must be 1 MB or less.  
2.2.3  
Notes on Using the JTAG (H-UDI) Clock (TCK) and AUD Clock (AUDCK)  
1. Set the JTAG clock (TCK) frequency to lower than the frequency of the SH7362 peripheral  
module clock (CKP).  
2. Set the AUD clock (AUDCK) frequency to 50 MHz or lower. If the frequency is higher than  
50 MHz, the emulator will not operate normally.  
3. The set value of the JTAG clock (TCK) is initialized by executing [Reset CPU] or [Reset Go].  
Thus the TCK value will be 1.25 MHz. When the [Search the best JTAG clock] option has  
been selected at initiation of the emulator, the TCK value is initialized to a value that was  
automatically acquired.  
2.2.4  
Notes on Setting the [Breakpoint] Dialog Box  
1. When an odd address is set, the next lowest even address is used.  
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.  
Accordingly, it can be set only to the RAM areas in CS0 to CS6 and the internal RAM areas.  
A BREAKPOINT cannot be set to the following addresses:  
ROM areas in CS0 to CS6  
Areas other than CS0 to CS6 except for the internal RAM  
A slot instruction of a delayed branch instruction  
An area that can be only read by MMU  
3. During step operation, BREAKPOINTs are disabled.  
4. When execution resumes from the address where a BREAKPOINT is specified, single-step  
operation is performed at the address before execution resumes. Therefore, realtime operation  
cannot be performed.  
5. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC  
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot  
instruction of a delayed branch instruction.  
6. Note on DSP repeat loop:  
A BREAKPOINT is equal to a branch instruction. In some DSP repeat loops, branch  
38  
 
instructions cannot be set. For these cases, do not set BREAKPOINTs. Refer to the hardware  
manual for details.  
7. When the [Normal] option is selected in the [Memory area] group box in the [General] page of  
the [Configuration] dialog box, a BREAKPOINT is set to a physical address or a virtual  
address according to the SH7362 MMU status during command input when the VPMAP_SET  
command setting is disabled. The ASID value of the SH7362 PTEH register during command  
input is used. When VPMAP_SET command setting is enabled, a BREAKPOINT is set to a  
physical address into which address translation is made according to the VP_MAP table.  
However, for addresses out of the range of the VP_MAP table, the address to which a  
BREAKPOINT is set depends on the SH7362 MMU status during command input. Even  
when the VP_MAP table is modified after BREAKPOINT setting, the address translated when  
the BREAKPOINT is set valid.  
8. When the [Physical] option is selected in the [Memory area] group box in the [General] page  
of the [Configuration] dialog box, a BREAKPOINT is set to a physical address. A  
BREAKPOINT is set after disabling the SH7362 MMU upon program execution. After setting,  
the MMU is returned to the original state. When a break occurs at the corresponding virtual  
address, the cause of termination displayed in the status bar and the [Output] window is  
ILLEGAL INSTRUCTION, not BREAKPOINT.  
9. When the [Virtual] option is selected in the [Memory area] group box in the [General] page of  
the [Configuration] dialog box, a BREAKPOINT is set to a virtual address. A BREAKPOINT  
is set after enabling the SH7362 MMU upon program execution. After setting, the MMU is  
returned to the original state. When an ASID value is specified, the BREAKPOINT is set to  
the virtual address corresponding to the ASID value. The emulator sets the BREAKPOINT  
after rewriting the ASID value to the specified value, and returns the ASID value to its original  
value after setting. When no ASID value is specified, the BREAKPOINT is set to a virtual  
address corresponding to the ASID value at command input.  
10. An address (physical address) to which a BREAKPOINT is set is determined when the  
BREAKPOINT is set. Accordingly, even if the VP_MAP table is modified after  
BREAKPOINT setting, the BREAKPOINT address remains unchanged. When a  
BREAKPOINT is satisfied with the modified address in the VP_MAP table, the cause of  
termination displayed in the status bar and the [Output] window is ILLEGAL INSTRUCTION,  
not BREAKPOINT.  
11. If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area, a  
mark z will be displayed in the [BP] area of the address on the [Source] or [Disassembly]  
window by refreshing the [Memory] window, etc. after Go execution. However, no break will  
occur at this address. When the program halts with the event condition, the mark z disappears.  
39  
 
2.2.5  
Notes on Setting the [Event Condition] Dialog Box and the BREAKCONDITION_  
SET Command  
1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Event  
Condition 3 are disabled.  
2. When an Event Condition is satisfied, emulation may stop after two or more instructions have  
been executed.  
3. If a PC break address condition is set to the slot instruction after a delayed branch instruction,  
user program execution cannot be terminated before the slot instruction execution; execution  
stops before the branch destination instruction.  
2.2.6  
Note on Setting the UBC_MODE Command  
In the [Configuration] dialog box, if [User] is set while the [UBC mode] list box has been set,  
Ch10 (IA_OA_R) and Ch11 (OA_OA_CT_R) of Event Condition cannot be used.  
2.2.7  
Note on Setting the PPC_MODE Command  
In the [Configuration] dialog box, if [User] is set while the [PPC mode] list box has been set, Ch1  
and Ch2 of the performance analysis function and options 1 and 2 of the profile function cannot be  
used.  
40  
 
2.2.8  
Performance Measurement Function  
The emulator supports the performance measurement function.  
1. Setting the performance measurement conditions  
To set the performance measurement conditions, use the [Performance Analysis] dialog box  
and the PERFORMANCE_SET command. When a channel line on the [Performance  
Analysis] window is clicked with the right mouse button, the popup menu is displayed and the  
[Performance Analysis] dialog box is displayed by selecting [Setting].  
Figure 2.8 [Performance Analysis] Dialog Box  
41  
 
Note: For the command line syntax, refer to the online help.  
(a) Specifying the measurement start/end conditions  
Set the performance measurement conditions in the [Action] page after conditions have been  
set in the [Event Condition] dialog box that is opened by double-clicking Ch1 to Ch6 and Ch8  
to Ch12 on the [Event Condition] sheet of the [Eventpoint] window.  
Notes: 1. When no measurement start/end conditions are specified, measurement is started by  
executing a program and ended when an event condition is satisfied.  
2. When only the measurement start or end condition is specified, performance cannot be  
measured. Be sure to specify both of the measurement start and end conditions.  
3. When the measurement start/end conditions are specified, step operation cannot be  
performed. In addition, when execution is restarted from the address where step  
operation has been stopped by the break conditions of BREAKPOINT or Event  
Condition, step functions are used and operation is disabled. Restart execution after  
the settings of the break conditions of BREAKPOINT or Event Condition have been  
canceled.  
4. It is not possible to specify the break conditions and the measurement start/end  
conditions at the same time with one channel. If the measurement start/end conditions  
are specified, the settings of the break conditions will be disabled.  
42  
 
Table 2.11 Conditions Specified in the [Action] Page  
Item  
Description  
PA1  
pa1_start_point  
pa1_end_point  
pa2_start_point  
pa2_end_point  
pa3_start_point  
pa3_end_point  
pa4_start_point  
pa4_end_point  
Specifies the conditions of Event Condition that has been set as  
the measurement start condition of performance channel 1.  
Specifies the conditions of Event Condition that has been set as  
the measurement end condition of performance channel 1.  
PA2  
PA3  
PA4  
Specifies the conditions of Event Condition that has been set as  
the measurement start condition of performance channel 2.  
Specifies the conditions of Event Condition that has been set as  
the measurement end condition of performance channel 2.  
Specifies the conditions of Event Condition that has been set as  
the measurement start condition of performance channel 3.  
Specifies the conditions of Event Condition that has been set as  
the measurement end condition of performance channel 3.  
Specifies the conditions of Event Condition that has been set as  
the measurement start condition of performance channel 4.  
Specifies the conditions of Event Condition that has been set as  
the measurement end condition of performance channel 4.  
43  
 
Figure 2.9 [Action] Page  
Note: PA1 or PA2 cannot be set for Ch8 and Ch9.  
44  
 
(b) Measurement tolerance  
The measured value includes tolerance.  
Tolerance will be generated before or after a break.  
For details, see table 2.14.  
(c) Measurement items  
Items are measured in the [Performance Analysis] dialog box for each channel from Ch1 to  
Ch4. A maximum of four conditions can be specified at the same time. Table 2.12 shows the  
measurement items. (Options in table 2.12 are parameters for <mode> of the  
PERFORMANCE_SET command. They are displayed in CONDITION of the [Performance  
Analysis] window.)  
45  
 
Table 2.12 Measurement Items  
Classification Type  
Measurement Item  
Option  
None  
AC  
Note  
Disabled  
Not measured.  
CPU  
Cycle  
Elapsed cycles  
Except for power-on period;  
counted by the CPU clock.  
performance  
Cycles executed in  
privileged mode  
PM  
BL  
I
The number of privileged-  
mode cycles among the  
number of elapsed cycles.  
Cycles for asserting  
the SR.BL bit  
The number of cycles when  
the SR.BL bit = 1 among the  
number of elapsed cycles.  
Instruction  
Number of effective  
instructions issued  
The number of execution  
instructions = number of valid  
instructions issued + number  
of cases of simultaneous  
execution of two instructions.  
The number of valid  
instructions means the  
number of completed  
instructions.  
Number of 2  
instruction executed  
simultaneously  
2I  
The number of times that two  
instructions are executed  
simultaneously among the  
valid instructions issued.  
Branch  
Number of  
unconditional branch  
BT  
The number of unconditional  
branches other than branches  
occurring after an exception.  
However, RTE is counted.  
Exception,  
interruption  
Number of  
exceptions accepted  
EA  
Interrupts are included.  
Number of interrupts INT  
accepted  
NMI is included.  
Number of UBC  
channel hit  
UBC  
Performs OR to count the  
number of channel-hits in the  
CPU.  
46  
 
Table 2.12 Measurement Items (cont)  
Classification Type Measurement Item  
Option  
Note  
CPU  
performance  
(cont)  
Stalled  
cycle  
Cycles stalled in full-  
trace mode (with  
multi-counts)  
SFM  
All items are counted  
independently.  
Cycles stalled in full-  
trace mode (without  
multi-counts)  
SF  
This item is not counted if the  
stall cycle is generated  
simultaneously with a stall  
cycle that has occurred due  
to instruction execution.  
TLB  
performance  
TLB  
Number of UTLB miss UMI  
for instruction fetch  
The number of TLB-miss  
exceptions generated by an  
instruction fetch (number of  
EXPEVT sets).  
Number of UTLB miss UMO  
for operand fetch  
The number of TLB-miss  
exceptions generated by an  
operand access (number of  
EXPEVT sets).  
Number of ITLB miss  
IM  
The number of ITLB misses  
for valid accesses (does not  
include UTLB hits or misses).  
Instruction bus Instruction  
performance  
Number of memory  
accesses for  
instruction fetch  
MIF  
The number of memory  
accesses by an instruction  
fetch.  
Accesses canceled by an  
instruction-fetch bus are not  
counted.  
Instruction fetches, which  
have been fetched in  
anticipation of a branch but  
not actually executed, are  
counted.  
Accesses by the PREFI  
instruction are included.  
Number of instruction  
cache access  
IC  
The number of accesses for  
an instruction cache during  
memory access of the  
opcode.  
47  
 
Table 2.12 Measurement Items (cont)  
Classification Type  
Measurement Item  
Option  
Note  
Instruction bus Instruction  
Number of  
instruction cache  
miss  
ICM  
The number of cache misses  
by an instruction cache  
access (the number of  
accesses to the outside of the  
CPU core due to a cache  
miss).  
performance  
(cont)  
(cont)  
Number of internal-  
RAM access for  
instruction fetch  
(XY-RAM or O-L  
memory)  
XL  
The number of accesses for  
the XY memory in the  
SH7362 during memory  
accesses of the opcode.  
Number of I-L  
memory access for  
instruction fetch  
ILIF  
ULF  
MR  
The number of accesses for  
the I-L memory in the SH7362  
during memory accesses of  
the opcode.  
Number of U  
memory access for  
instruction fetch  
The number of accesses for  
the U memory in the SH7362  
during memory accesses of  
the opcode.  
Operand bus  
performance  
Access  
count  
Number of memory  
access for operand  
fetch (READ)  
The number of memory  
accesses by an operand read  
(equal to loading on the  
operand bus).  
Accesses by the PREF  
instruction or canceled  
accesses are not included.  
Number of memory  
access for operand  
fetch (WRITE)  
MW  
The number of memory  
accesses by an operand write  
(equal to storing memory on  
the operand bus).  
Canceled accesses are not  
included.  
Number of operand  
cache access  
(READ)  
CR  
The number of operand-  
cache reads during memory  
access (read) of an operand.  
Number of operand  
cache access  
(WRITE)  
CW  
The number of operand-  
cache reads during memory  
access (write) of an operand.  
48  
 
Table 2.12 Measurement Items (cont)  
Classification Type Measurement Item  
Option  
Note  
Operand bus  
performance  
(cont)  
Access  
Number of internal-  
count (cont) RAM access for  
operand fetch  
XLR  
The number of accesses to XY  
memory in the SH7362 during  
memory access (read) of an  
operand.  
(READ) (XY-RAM or  
O-L memory)  
(Accesses via the XY bus and  
the operand bus are included.  
When MOVX and MOVY are  
executed simultaneously, it  
increments one count  
regardless of the read or write.)  
Number of internal-  
RAM access for  
operand fetch  
(WRITE) (XY-RAM  
or O-L memory)  
XLW  
The number of accesses to XY  
memory in the SH7362 during  
memory access (write) of an  
operand.  
(Accesses via the XY bus and  
the operand bus are included.  
When MOVX and MOVY are  
executed simultaneously, it  
increments one count  
regardless of the read or write.)  
Number of I-L  
memory access for  
operand fetch  
ILRW  
UR  
The number of accesses to I-L  
memory in the SH7362 during  
memory access (read/write) of  
an operand.  
(READ/WRITE)  
Number of U-RAM  
access (READ)  
The number of U-memory  
accesses during memory  
access (read) of an operand.  
(Accesses via the cache are  
not included.)  
Number of U-RAM  
access (WRITE)  
UW  
The number of U-memory  
accesses during memory  
access (write) of an operand.  
(Accesses via the cache are  
not included.)  
49  
 
Table 2.12 Measurement Items (cont)  
Classification Type Measurement Item  
Option  
Note  
Operand bus  
performance  
(cont)  
Access  
miss count  
Number of operand  
cache miss (READ)  
CMR  
The number of cache misses  
by an operand cache access  
(read) (number of accesses to  
the outside of the CPU core  
due to a cache miss).  
Cache misses are not counted  
by the PREF instruction.  
Number of operand  
cache miss (WRITE)  
CMW  
The number of cache misses  
by an operand cache access  
(write) (number of accesses to  
the outside of the CPU core  
due to a cache miss).  
Write-through accesses are not  
counted.  
Cache misses are not counted  
by the PREF instruction.  
Number of U-RAM  
read-buffer miss  
UBM  
Waited  
cycle  
Waited cycles for  
operand fetch  
(READ)  
WOR  
The number of wait cycles by a  
memory access (read) of an  
operand.  
Waited cycles for  
operand fetch  
(WRITE)  
WOW  
The number of wait cycles by a  
memory access (write) of an  
operand.  
Waited cycles for  
operand cache miss  
(READ)  
WCMR  
The number of wait cycles by  
an operand cache miss (read)  
(however, the number of wait  
cycles of cache FIII is included  
due to contention).  
Waited cycles for  
operand cache miss  
(WRITE)  
WCMW  
The number of wait cycles by  
an operand cache miss (write).  
Waited cycles for I-L WILR  
access (READ)  
The number of wait cycles by I-  
L memory access (READ) of  
an operand.  
Waited cycles for I-L WILW  
access (WRITE)  
The number of wait cycles by I-  
L memory access (WRITE) of  
an operand.  
50  
 
Table 2.12 Measurement Items (cont)  
Classification Type Measurement Item  
System bus Number of requests  
Option  
Note  
System bus  
performance  
(only available  
for Ch3 and  
Ch4)  
RQ  
The number of valid bus cycles  
(cells) is counted by the  
system bus clock.  
Number of  
responses  
RS  
The number of valid bus cycles  
(cells) is counted by the  
system bus clock.  
Waited cycles for  
request  
WRQ  
The cycles for an issued  
request (req), that no  
acceptance signal (gnt) is  
issued to, are counted by the  
system bus clock.  
Even if the waits are issued  
simultaneously for multiple  
requests, they are counted as  
1.  
Waited cycles for  
response  
WRS  
The cycles for an issued  
response (r_req), that no  
acceptance signal (r_gnt) is  
issued to, are counted by the  
system bus clock.  
Even if the waits are issued  
simultaneously for multiple  
requests, they are counted as  
1.  
51  
 
Table 2.13 shows the measurement items and methods that are mainly used.  
Table 2.13 Main Measurement Items  
Main Measurement Item  
Elapsed time  
Measurement Method  
Number of elapsed cycles x CPU clock cycles  
Number of execution instructions  
Number of valid instructions issued + number of cases of  
simultaneous execution of two instructions  
Number of interrupts accepted  
Number of exceptions accepted  
Number of instruction fetches (for  
both cache and non-cache)  
Number of memory accesses in an opcode  
Instruction-cache hit ratio  
(Number of instruction-cache accesses– instruction-cache  
miss counts)/instruction-cache access counts  
Number of operand accesses (for  
both cache and non-cache)  
Number of memory accesses in an operand (read) + number  
of memory accesses in an operand (write)  
Operand-cache hit ratio (read)  
Operand-cache hit ratio (write)  
Operand-cache hit ratio  
(Number of operand-cache accesses (read) – number of  
operand-cache misses (read))/number of operand-cache  
accesses (read)  
(Number of operand-cache accesses (write) – number of  
operand-cache misses (write))/ number of operand-cache  
accesses (write)  
(Number of operand-cache accesses (read) + number of  
operand-cache accesses (write) – number of operand-cache  
misses (read) – number of operand-cache misses  
(write))/(number of operand-cache accesses (read) + number  
of operand-cache accesses (write))  
System bus: occupied rate of  
request bus  
(The equivalent CPU clock value of the number of  
requests)/number of elapsed cycles  
System bus: occupied rate of  
response bus  
(The equivalent CPU clock value of the number of  
responses)/number of elapsed cycles  
52  
 
Each measurement condition is also counted when conditions in table 2.14 are generated.  
Table 2.14 Performance Measurement Conditions to be Counted  
Measurement Condition  
Notes  
No caching due to the  
settings of TLB cacheable  
bit  
Counted for accessing the cacheable area.  
Cache-on counting  
Accessing the non-cacheable area is counted less than the actual  
number of cycles and counts. Accessing the cacheable, X/Y-RAM,  
and U-RAM areas is counted more than the actual number of cycles  
and counts.  
Branch count  
The counter value is incremented by 2. This means that two cycles  
are valid for one branch.  
Notes: 1. In the non-realtime trace mode of the AUD trace and memory output trace, normal  
counting cannot be performed because the generation state of the stall or the execution  
cycle is changed.  
2. Since the clock source of the counter is the CPU clock, counting also stops when the  
clock halts in the sleep mode.  
(d) Extension setting of the performance-result storing counter  
The 32-bit counter stores the result of performance, and two counters can be used as a 64-bit  
counter.  
To set a 64-bit counter, check the [Enable] check box in the [Extend counter] group box of the  
[Performance Analysis] dialog box for Ch1 and Ch3.  
2. Displaying the result of performance  
The result of performance is displayed in the [Performance Analysis] window or the  
PERFORMANCE_ANALYSIS command in hexadecimal (32 bits).  
However, when the extension counter is enabled, it is displayed in hexadecimal (64 bits).  
Note: If a performance counter overflows as a result of measurement, “********” will be  
displayed.  
3. Initializing the measured result  
To initialize the measured result, select [Initialize] from the popup menu in the [Performance  
Analysis] window or specify INIT with the PERFORMANCE_ANALYSIS command.  
53  
 
54  
 
SuperHFamily E10A-USB Emulator  
Additional Document for User's Manual  
Supplementary Information on Using the SH7362  
Publication Date: Rev.1.00, August 20, 2007  
Published by:  
Sales Strategic Planning Div.  
Renesas Technology Corp.  
Customer Support Department  
Global Strategic Communication Div.  
Renesas Solutions Corp.  
Edited by:  
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.  
 
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SuperHFamily E10A-USB Emulator  
Additional Document for User’s Manual  
Supplementary Information  
on Using the SH7362  
 

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